1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a transistor. More particularly, the present invention relates to a method of manufacturing a semiconductor device that includes an improved transistor of which carriers rapidly move in a channel region under a gate electrode thereof.
2. Description of the Related Arts
In recent years, as information media such as a computers enjoy widespread use, semiconductor devices continue to develop at a rapid pace. in general, semiconductor devices with rapid operation speeds and a large amount of memory are desired. To meet these requirements, semiconductor manufacturing technology must keep pace to continuously improve integration degree, reliability, response speed, etc., of semiconductor devices.
To improve the response speed of the semiconductor device, a material for reducing parasitic capacitance is employed in wiring of the semiconductor device. In addition, a reduction in sheet resistance and contact resistance between a gate electrode and source/drain regions can have beneficial effects. To reduce the sheet resistance and the contact resistance, a metal silicide layer having a lower specific resistance is selectively formed on surfaces of the gate electrode and the source/drain regions corresponding to an interface between a polysilicon layer and a substrate. Here, examples of the metal silicide layer include a titanium silicide layer, cobalt silicide layer, tungsten silicide layer, etc. Particularly, the technology for forming the metal silicide layer is used for improving characteristics of a gate electrode of a dynamic random access memory (DRAM) having a storage capacity of no less than about one gigabite, and other devices, including logic devices, merged memory logic (MML), and the like.
FIGS. 1A to 1C are cross sectional views illustrating a conventional method of forming a CMOS transistor including a metal silicide layer.
Referring to FIG. 1A, a semiconductor substrate 10 having an N type metal oxide semiconductor (MOS) transistor and a P type MOS transistor is provided. An isolation layer 12 partitions the semiconductor substrate 10 into an N type MOS transistor formation region and a P type MOS transistor formation region.
The P type MOS transistor 20a includes a gate electrode 14a, source/drain regions 18a having lightly doped drain (LDD) structures in which P type impurities are doped, a spacer 16 formed on a sidewall of the gate electrode 14a, and a channel region (not shown). The N type MOS transistor 20b includes a gate electrode 14b, source/drain regions 18b having a lightly doped drain (LDD) structure in which N type impurities are doped, the spacer 16 formed on a sidewall of the gate electrode 14b, and a channel region (not shown).
Referring to FIG. 1B, a metal layer 22 is formed on the P type MOS transistor, the N type MOS transistor and the semiconductor substrate 10. The metal layer 10 is thermally treated at a temperature of about 450° C. to form a preliminary metal silicide layer (not shown). Any remaining metal layer that does not react with an underlying metal material is then removed.
Referring to FIG. 1C, the preliminary metal silicide layer is additionally thermally treated at a temperature of about 850° C. to form a metal silicide layer 24 having a low resistance, thereby completing the transistors 20a, 20b on the substrate 10.
The metal silicide layer 24 reduces sheet resistance and contact resistance of the gate electrodes 14a and 14b and the source/drain regions 18a and 18b, respectively, so that performance of the transistors may be improved.
However, as critical dimensions of the gate electrode and the source/drain regions continue to decrease due to the trend toward ever higher integration of semiconductor devices, forming crystalline germs of metal silicide that is formed by a chemical reaction between metal and silicon becomes increasingly difficult so that external resistance factors are increased. The external resistance factors cause a corresponding increase of resistance and cohesion of metal silicide in the gate electrode and the source/drain regions, thereby deteriorating the performance of the resulting N type MOS transistor 20a and the P type MOS transistor 20b. In particular, the performance of the P type MOS transistor may be even more adversely affected in comparison with the N type MOS transistor.